1. Field of the Invention
This invention relates generally to system on a chip integrated circuits. More particularly, it relates to an apparatus and technique for monitoring internal bus functions of an integrated circuit without requiring additional external pins on the integrated circuit.
2. Background of Related Art
One of the biggest problems faced by system on a chip designers is the ability to monitor what is going on inside the system.
One conventional solution is to provide additional external pins on the device corresponding to selected internal nodes of the system. However, system on a chip integrated circuits are typically already PAD limited, and typically already have a very high external pin count. Moreover, even if one has the opportunity to provide additional external pins, doing so adds cost to the manufacturing of the integrated circuit.
FIG. 8 shows a block diagram of a conventional system on a chip integrated circuit.
In particular, in FIG. 8, an integrated circuit 850 is formed including a plurality of devices communicating via an internal bus 810. For instance, as shown in FIG. 8, an appropriate processor (e.g., microprocessor, microcontroller, or digital signal processor (DSP)) controls a system including, e.g., SRAM and/or ROM 802 connected to a memory socket (MEM).
Such a system on a chip typically further includes an internal bus 810 connected to the processor, e.g., through an internal El socket. The internal bus 810 may have any application specific components in communication therewith, e.g., a direct memory access controller (DMAC) 806, an Ethernet MAC 808, a Universal Serial Bus (USB) 818, a peripheral Components Interface (PCI) interface 812, a high speed input/output (HSIO) device 814, and/or an external memory interface 816.
As shown in FIG. 8, some of the components may have pins or busses passing through external to the integrated circuit, e.g., the Ethernet MAC 808, the USB 818, the PCI 812, the HSIO 814, and/or the EMI 816. For instance, the EMI interface 816 is shown in FIG. 8 connected to an external bus accessing external SDRAM 830 and external ROM 832.
FIG. 9 shows waveforms showing exemplary cycles of activity on an internal bus 810 of a conventional system on a chip.
For instance, a system clock signal is shown in waveform (a) of FIG. 9. Activity on an address bus is shown in waveform (b). A chip select signal (CS) to a particular bus device (e.g., the EMI 816) is shown in waveform (c). Associated data (e.g., data OUT) is shown in waveform (d) in relation to the address bus and chip select signal.
Waveform (e) of FIG. 9 depicts the various cycles of the internal bus 810. During a setup cycle 910, the chip select signal (waveform (c)) to the appropriate device is presented to the internal bus 810, and the address on the internal bus 810 is allowed to settle. The length of the setup cycle 910 is.often dictated by the speed of the device being accessed, e.g., memory.
After setup, the now valid address on the address bus (waveform (b)) is decoded by the various circuitry to determine the particular device being addressed. The addressed device responds with the appropriate data as shown in waveform (d).
After the data settles on the internal bus 810 by the end of the decode cycle 912, access to the addressed data is performed during an access cycle 914.
The internal bus 810 typically remains idle during the time after access is performed in the access cycle 914 and before the next setup cycle begins. This is referred to herein as an idle cycle 916.
Systems on a chip are compact devices offering miniaturization to designers. However, systems on a chip are extremely difficult to debug during development, in part because of the limitations on the signals available external to the integrated circuit.
For instance, the actual activity on the internal bus 810 of the system is not directly observable by a designer, but rather must be inferred by observations made in memory, registers, etc. However, these inferences do not always allow distinctions to be made between subtle actions which occur during the various cycles of the internal bus 810. Because of this, conventional debugging systems are limited to connections to exploration of external RAM memory, e.g., the external SDRAM 830, to view changes as a system is operated within the integrated circuit. This requires inferences to be made on the part of the system debugger, ultimately slowing down the debugging process.
There is a need for an improved technique and method for monitoring internal functions of a system on a chip, e.g., for the purposes of debugging a system design.
In accordance with the principles of the present invention, a state generator comprises a plurality of memory access cycles within a single memory access. A system debugging snoop cycle is adapted for insertion between two of the plurality of memory access cycles to allow pass through of activity on an internal bus controlled by the state generator through a device communicating over the bus.
A method of passing internal bus data through a component of a system on a chip integrated circuit in accordance with another aspect of the present invention comprises inserting a snoop cycle in a memory access, and directly passing activity on an internal bus internal to the system on a chip integrated circuit to an external bus of a snooping pass through device during the snoop cycle.